The present invention generally relates to electronic circuits, and, more particularly, to a system for compensating for variations in the frequency of clock signals used in electronic circuits.
Electronic circuits including microprocessors, microcontroller units (MCUs), digital signal processors (DSPs), application specific integrated circuits (ASICs), and systems-on-chips (SOCs) often perform functions such as storing or retrieving data that require synchronizing the data with clock signals. An external clock source, such as a crystal oscillator or a clock generator, generates and provides a clock signal having a predefined operating frequency to the electronic circuit. The accuracy of the clock signal determines the efficiency of the electronic circuit. However, due to certain external factors, such as excess voltage, aging, temperature rise, and overheating, delays are introduced in the clock signals that can cause the circuits to process data improperly, resulting in faulty outputs. For example, if the electronic circuit is used in time critical applications such as medical applications, any inaccuracy or delay in the clock signal may introduce delays in the treatment time, which may lead to serious consequences. Therefore, frequency variations, i.e., the delays in the clock signals, need to be compensated for or corrected.
Frequency variations or delays in a clock signal usually have two components, viz., a coarse (or integer) delay component and a fine (or fractional) delay component. In conventional delay compensation solutions, the fine delay is accumulated over a predetermined compensation interval to compensate for a single coarse delay over the predetermined time interval. For power critical applications, this delay adjustment is performed using a low frequency clock. However, a low frequency clock fails to provide an accurate edge placement on the output clock that is generated. Applications requiring a reference output clock signal for calibration take longer as the compensation interval is not always unit time (one second) and does not have accurate rise or fall edge placement. Therefore, to compensate for the fine part in a single 1 Hz period, a fast clock (i.e., a high frequency clock) is necessary. High frequency clocks increase power consumption and operating cost, which is not desirable for applications that run on batteries or those which are power-critical.
Conventional delay compensation solutions assume a variable-length one-second period in a predetermined time period counted by the real time clock (RTC). The length (or duration) of a variable-length second period is changed once for each predetermined time period. By changing a time-correction coefficient, the variable-length one-second period can insert at least one 32 kHz clock cycle in each predetermined time period interval. Delays in clock signals are also compensated in small intervals of time instead of for every one second interval. For example, a clock delay or a frequency offset may be accumulated and compensated every fifteen seconds using known methods of delay compensation. However, compensating every fifteen seconds may not be suitable for time-critical applications. although conventional techniques compensate for the delay at periodic intervals, they fail to compensate for the delay introduced in each unit of output clock cycle.
Many time-critical electronic circuits require an accurate 1 Hz clock signal that is generated using a 32.768 kHz clock generator. The clock generator counts 0 to 32,767 pulses to generate a 1 Hz clock signal that includes 32,768 pulses. However, when a frequency variation is introduced in the 32.768 kHz clock signal, the number of pulses either increases or decreases from the expected value of 32,768. For example, if the clock generator counts 32,769.146 pulses, a delay of 1.146 pulses (i.e., 32,769.146-32,768 pulses) is introduced. For the 1.146 pulse delay, ‘1 pulse’ forms the coarse delay component and ‘0.146 pulse’ forms the fine delay component. However, there presently is no solution to compensate for the fine frequency variations in each unit output cycle of the clock generator. Conventional delay compensation solutions require the predetermined interval to be more than one second to allow the fine part to be factored into the coarse compensation. For example, a 0.146 pulse delay would lead to a coarse value of −39 and a predetermined interval of 34 seconds. Thus, for every 34 seconds, there is a one second period that is shorter by 39 ticks of the 32.769.146 Hz clock signal.
It would therefore be advantageous to have a system that compensates for clock delay every unit output cycle of the clock generator, that switchably provides coarse and fine delay compensation, has low power consumption, and overcomes the above-mentioned shortcomings of the existing clock delay compensation systems.